1. Field of the Invention
The present invention is directed to logic configurations and, more particularly, to logic configurations that may be used to enhance the performance characteristics of fabricated devices.
2. Description of the Background
It is known in the art that circuits having ideal characteristics are rarely achieved because of process variations in the fabrication process. For example, in a CMOS process, one xe2x80x9cpassxe2x80x9d of the process may result in fast NMOS transistors and slow PMOS transistors while another xe2x80x9cpassxe2x80x9d of the process may result in just the opposite. Having NMOS and CMOS transistors that are matched, however, is a very important aspect of circuit design because many logic circuits are designed to operate in a balanced mode, i.e. signals must propagate through paths constructed of n-channel devices and paths of p-channel devices at the same speeds relative to each other.
For example, clock signals are commonly used in digital circuits, including circuits used in memory devices, to control the timing at which various event occur. In some cases, a single clock signal is used. However, in other cases, it is necessary to use both the clock signal and the complement of the clock signal. Such signals are typically generated by applying a clock signal to a phase splitter, which then generates a clock signal and its complement for use by the digital circuit.
It is important that the clock signal and its complement be symmetrical, i.e., the edges of both signals be substantially aligned and have the same slew rate. The clock signal and its complement generated by an ideal phase splitter would have a 50 percent duty cycle, equal rise and fall times, and they would be exactly 180 degrees out of phase from each other. In practice, that ideal is rarely achieved. As a result, the inverters comprising the phase splitter respond differently to an incoming clock signal, and the respective clock signals generated by the inverters are not symmetrical.
A conventional phase splitter 10 is illustrated in FIG. 1. The phase splitter 10 includes two branches 12, 14, one of which generates a signal OUT and the other of which generates its complement OUT*. The second branch 14 consists of three inverters 16, 18, 20. Because there is an odd number of inverters in the second branch 14, the output signal OUT* is the complement of the input signal CLK, but delayed in time by the sum of the propagation delays through each of the inverters 16, 18, 20.
The first branch 12 consists of two inverters 22, 24 and a capacitor 26 connected to the output of the first inverter 22. The size of the capacitor 26 is selected to delay the coupling of signals from the output of the first inverter 22 to the input of the second inverter 24 by an amount corresponding to the difference between the delay of the three inverters 16, 18, 20 and the two inverters 22, 24. As a result, the OUT signal and the OUT* signal are theoretically 180 degrees out of phase with each other. In practice, however, the OUT and OUT* may not be entirely symmetrical for several reasons. For example, although the capacitor 26 compensates for the delay of the extra inverter in the second branch 14 it also reduces the slew rate of the signal applied to the input of the inverter 24. As a result, the slew rate of the signal applied to the inverter 24 is substantially slower than the slew rate of the signal applied to the inverter 20. That difference in slew rates causes the rise and fall times of the signals OUT and OUT* to differ substantially from each other.
Proposals have been made to modify the phase splitter 10 shown in FIG. 1 by eliminating the capacitor 26 and instead adjusting the delay of each of the inverters 16, 18, 20, 22, 24 to achieve substantially the same result. More specifically, the inverters 16, 18, 20 may be designed so that the sum of the delays through the inverters 16, 20 is equal to the delay through the inverter 22. The inverters 18 and 24 are then designed so that they have equal propagation delays. As a result, the signals OUT and OUT* are, in theory, symmetrical. Again, in practice, the signals are anything but symmetrical for several reasons. For example, the inverters 16, 20 must be relatively fast so that the sum of their delays is equal to the delay of the inverter 22. The high speed of the inverter 20 causes it to have a relatively high slew rate. For the slew rate of the OUT signal to match the slew rate of the OUT* signal, the transistors used in the inverter 24 must be relatively large. However, the inverter 22 must be fairly slow to achieve the required delay, and, as a result, its output signal has a relatively low slew rate. The low slew rate of the inverter 22 makes it all the more difficult for the output of the inverter 24 to match the output of the inverter 20 so that OUT and OUT* will have the same rise and fall times.
Another example is a phase locked loop. A phase locked loop (PLL) is a circuit designed to minimize the phase difference between two signals. When the phase difference approaches zero, or is within a specified tolerance, the phase of the two signals is said to be xe2x80x9clockedxe2x80x9d. A delay locked loop (DLL) is similar to a phase locked loop, but instead of producing an output signal which has the same phase as an input or reference signal, the delay locked loop produces an output signal that has some predefined phase delay with respect to a reference or input signal.
PLL""s and DLL""s are used in a variety of devices where the PLL or DLL must be constructed of all digital components. For example, all digital implementations of PLL""s and DLL""s are needed for such complex circuits as high speed memory devices. The local clock of certain types of memory devices needs to be in sync with, for example, a data bus so that data may be reliably written to or read from the bus. PLL""s and DLL""s are also needed when transferring data within the memory device to insure, for example, that data read out of the memory is properly presented to output pads. The paths used to construct PLL""s and DLL""s typically have a plurality of series connected inverters. As previously discussed, it may be difficult to achieve a balanced relative delay for both n-channel and p-channel transistor paths over process and condition variations. Thus, a need exits for a hardware solution that can be implemented in any number of logic circuits to compensate for fabrication process variations
The present invention is directed to a compensation circuit which includes at least one of an n-channel device connected to oppose a high-to-low transition and a p-channel device connected to oppose a low-to high transition. The n-channel and p-channel devices may be diodes, transistors, or transistors connected to function as diodes. The n-channel and p-channel devices may be connected to a large variety of devices and circuits, such as phase locked loops, delay locked loops, clock circuits, or any circuit which requires two balanced paths, one through n-channel devices and one through p-channel devices, to compensate for process variations.
The present invention is also directed to a method for balancing a circuit path, comprising providing biasing an output terminal at a predetermined value to provide a resistance to transitions from a high to a low state and from a low to a high state. The voltage for the biasing step may be provided by a device in the circuit path or by a voltage source.
The method and apparatus of the present invention provide compensation for process variations between n-channel devices and p-channel devices in a simple and effective manner implemented by adding a minimal number of components to existing circuits. Those advantages and benefits, and others, will be apparent from the Description of the Preferred Embodiment hereinbelow.